In semiconductor memory devices that have a matrix of memory cells, data is usually carried to and from the memory cells by pairs of data lines. During a read process, data is read from the memory cells through the data lines and a series of components to the output of the memory device. During a write process, data is transferred from the input of the semiconductor memory device through the data lines and the series of components to the memory cells.
An exemplary semiconductor memory device that shows read and write processes is shown in U.S. Pat. No. 5,598,376, to Merritt et al. Merritt et al. discloses distributed write data drivers for burst access memories. With reference to FIG. 4 of Merritt et al., data written to the memory device is received on data I/O pad 100. The write data is passed through input circuit 102 to a global sense amp 66 over write data lines 103. The sense amplifier includes an I/O line multiplexer 104 which is used to select a path from local I/O data line pair 106 to one of two pairs of array I/O lines 108 and 110. I/O lines 108 are coupled to an adjacent section of the array (not shown). Array I/O lines 110 are true and complement lines coupled to a local array sense amplifier 112 which is part of array section 64. Column select signal 114 from column driver 115 couples array data I/O lines 110 to a pair of complementary lines 116 inside the local sense amplifier 112. Read data follows the same path from the memory cell to the global sense amp 66, where it is then driven on complementary data read lines 122 to complementary data lines 126 under control of data path control logic 124 and timing circuits 59. Data is driven to I/O pad 100 through output circuit 128.
Thus, Merritt et al. uses different sets of lines for its read and write operations. As described above, write data is passed to the global sense amp 66 over write data lines 103, which is different than the path of the read data from the global sense amp which travels over complementary read data lines 122 and 126. This is a common prior art method that uses different physical lines for the write and read data paths. A distinct disadvantage of this method relative to a method using the same data lines for both read and write processes is that it requires more control circuitry and more wiring, and thus consequently requires more area.
FIG. 2 of Merritt et al. illustrates some timing diagrams for a circuit such as that shown in FIG. 4. Specifically, FIG. 2 illustrates timing diagrams for performing a burst read followed by a burst write. As shown in FIG. 2, when the CAS signal is low the WE signal is high, a burst read access is started. On the second following edge of the CAS signal, the internal address generation circuitry provide a column address, and another access of the array begins. The first data out is driven from the device following the second CAS signal. Additional burst access cycles continue, for a device with a specified burst length of four, until the fifth following edge of CAS which latches a new column address for a new burst read access. The WE signal following in the fifth CAS cycle terminates the burst access, and initializes the device for additional burst accesses. The sixth following edge of CAS when the WE signal is low is used to latch a new burst address, latch input data, and begin a burst write access of the device. Additional data values are latched on successive CAS following edges until the RAS signal rises to terminate the burst access.
As illustrated in the timing diagrams of FIG. 2, Merritt et al. uses a burst access process for both read and write operations. This is done to achieve a faster, random access memory circuit. However, while this method of Merritt et al. works well in a system where the read and write operations are performed using different data lines, it does not address the problem of how to do faster reads and writes in a system that uses the same lines for both read and write operations. In particular, the timing diagrams of FIG. 2 do not address the problem of how to quickly transmit write data over lines that are controlled by read timing cycles. In systems which use the same lines for read and write operations, this problem must be addressed in order for the read and write operations to be performed. One prior art method for addressing this problem is to disable all the timing clocks that were used for the read process when a write process is to be performed. A disadvantage of this method is that then the write timing is not related to the read timing in any way and thus under certain conditions the write or read processes may break, and random reads or writes will not be possible at faster speeds.
The present invention is directed to providing a memory device that overcomes the foregoing and other disadvantages. More specifically, the present invention is directed to a memory device for performing a write operation within the same clock timing as the read.